1. Field of the Invention
The present invention relates to the field of computer graphics and more particularly to the field of displaying objects on the screen of a display device.
2. Description of the Prior Art
Computer graphics systems for displaying objects on the screen of a display device require very rapid processing of large amounts of data to enable the displayed object to be moved or shading of the surface of the object to vary with variations in the location of a source of light that is shining on the object. This need for rapid computation has resulted in reduction of the time required to specify the object to be displayed in terms of the many points or vertices that are used to define the surface of the object. With the location of such points defined, when the display device is a cathode ray tube (CRT), the next step in displaying the object is to rapidly convert such points into data indicating which picture elements ("pixels") on the screen of the CRT must be illuminated or turned ON in order to display the object. This involves the steps of processing pairs of vertices that define a line. The processing indicates which pixels on the screen must be turned ON to draw the line between the pairs of vertices. Also, because the screen may have hundreds of pixels in each of the x and y coordinate directions (such as 1280 by 1024), the data defining which pixels must be turned ON must be stored in a manner suitable for controlling the video function of the CRT. For example, when the CRT functions on a scan line by scan line basis as is customary, the manner in which the pixels of the screen are processed for drawing lines and for data storage purposes must be specially related to the scan lines so as to minimize storage requirements without reducing the speed of the scanning operation.
To achieve some of these objectives, in the past the screen of the CRT has been divided into blocks, where each block has a given row address (a DRAM row address) within a DRAM chip that stores the pixel ON data. Such blocks of the screen have been related to column addresses within the DRAM (DRAM column addresses), such as by having a given screen block for a given DRAM row address extend 128 DRAM column addresses in the x direction on the screen and two rows of screen blocks in the y direction on the screen. To reduce the number of times that a given line drawn on the screen of the CRT requires a new DRAM row address (which slows down addressing), others have related the DRAM row addresses to the screen blocks more symmetrically by providing, for a given DRAM row address, a screen block that extends in the x direction 16 columns and 16 columns in the y direction. As a result, regardless of the direction of the line, it is more likely that the line will extend through more DRAM column addresses before a new DRAM row address must be addressed.
Having reduced the number of times that a new DRAM row address is required as the line is drawn from screen block to screen block, others have then organized the pixels within a given screen block into groups, such as groups of 64 pixels formed by 8 pixels in the x direction on the screen and 8 pixels in the y direction on the screen. Others have used groups of 20 pixels formed by groups of 5 pixels in the x direction and 4 pixels in the y direction. Such group of pixels has been referred to as a "matrix". Each matrix in a given screen block has a specific DRAM column address and has the DRAM row address common to the entire screen block.
Such pixel group or matrix has been used in the past to define a unit or group of pixels that are written into the DRAM at the same time. Initially, the determination of which pixel out of the 20 pixels in such 5 by 4 matrix will be ON has been performed on a pixel-by-pixel basis using a number of machine cycles, where one machine cycle occurs for every one clock cycle of a bit slice processor, for example. Once the pixel-by-pixel determination has been completed for all of the pixels in the matrix, then the entire matrix, representing the pixels that should be ON and OFF of the group of 20 pixels, is written into the DRAM in one or more additional machine cycles. In this approach, there is no need to determine which matrix the line will extend into next (the "next matrix") during the computation of the pixels for a particular or ("current") matrix. Rather, only when the next "ON" pixel of the next matrix is identified is the next matrix identified. This occurs after the writing of the current matrix into the DRAM. In this prior method, it may be understood that it required 5 machine cycles to identify the 5 pixels that must be turned on in order to have a line completely cross a given matrix. Thus, 5 machine cycles were required to identify such 5 ON pixels and one (or more) additional cycle to write them into the DRAM.